In accordance with recent developments in technologies, power supply terminals and signal terminals in LSI (Large Scale Integrated Circuit) have been developed into multi-terminals due to the increasing information amount handled therewith and the tendency of having low voltage and high power. Methods for connecting LSI having several tens to several hundreds of terminals to a target board (printed circuit board, interposer, etc.) may be soldering using solder or the like, and adhesion using a conductive binder.
With such connecting methods, when the width of the clearance between the connected LSI and the target board becomes nonuniform, load is concentrated onto a part of the connected area. This may result in having a poor connection state, so that it is necessary to level the width of the clearance between the soldered LSI and the target board. This will be described in a specific manner by referring to drawings.
FIG. 62 shows a schematic sectional view of a state where the clearance between the LSI and the target board is nonuniform. An LSI 300 shown in FIG. 62 includes an interposer 310, a semiconductor circuit chip 330, and LSI pads 320 used for connection. A printed circuit board 400 as the target board includes PWB pads 420 used for connection. Wirings of the interposer 310 and the wirings of the printed circuit board 400 are omitted in the drawings.
If the LSI 300 is tilted when mounting the LSI 300 to the printed circuit board 400, a section 901 having a large clearance width with respect to the printed circuit board 400 and a section 902 having a small clearance width are generated. Thus, solder 501 which is supposed to connect the LSI pads 320 to the PWB pads 420 is separated from one of the pads in the section 901 having the large clearance width, thereby causing a poor connection state 903.
In order to avoid such poor connection state, Patent Document 1 discloses a technique which prevents the clearance width between the target board and the electronic component from becoming nonuniform.
FIG. 63 shows a side view as well as a bottom view of a semiconductor device 4 depicted in Patent Document 1, and a side view when it is mounted to a device board. The technique disclosed in Patent Document 1 makes the width of the clearance between the semiconductor device 4 and the device board 2 by supporting the semiconductor device 4 and the device board 2 by a spacer 42.
However, with the technique disclosed in Patent Document 1, the spacer 42 is provided in the outer fringe part of the semiconductor device 4. For that, the external size of the semiconductor device 4 is expanded more than it is necessary, thereby increasing the occupying area. Further, since the spacer 42 is unified with the semiconductor device 4, there is no versatility in the clearance width between the semiconductor device 4 and the device board 2 when mounting the semiconductor device 4. Thus, the soldering condition such as the size of solder balls 15 cannot be changed easily.
Patent Document 2 therefore discloses a technique which overcomes the inconveniences of the technique disclosed in Patent Document 1, and Patent Document 3 discloses a capacitor that is suited for an electronic component depicted in Patent Document 2.
FIG. 64 shows a bottom view and a side view of the semiconductor device depicted in Patent Document 2. With the technique disclosed in Patent Document 2, electronic components 54 are attached in advance between solder balls 53 provided on the bottom face of a base board 52 so as to support the base board 52 and a mother board with the electronic components 54 when mounting the base board 52 to the mother board to have a uniform width of the clearance between the base board 52 and the mother board. With this structure, the size of the base board 52 can be remained in a normal size.
FIG. 65 shows a perspective view and a sectional view of the capacitor depicted in Patent Document 3. The capacitor shown in FIG. 65 is formed in a structure in which electrodes 61, 62, 63, and 64 are disposed at four corners or the like. It is possible to have a capacitance between terminals of the base board 52 by using such capacitor as the electronic component 54 depicted in Patent Document 2 to connect the electrodes 61, 62, 63, and 64 with solder.
Patent Document 1: Japanese Unexamined Patent Publication H8-316268 (FIG. 1)
Patent Document 2: Japanese Unexamined Patent Publication 2004-273475 (FIG. 1)
Patent Document 3: Japanese Unexamined Utility Model Publication S63-157919 (FIG. 1 and FIG. 2)